#ifndef HARDWARE_MILSTD_H_
#define HARDWARE_MILSTD_H_

typedef struct
{
	volatile unsigned cfg;
	volatile unsigned bcAddr;
	volatile unsigned ctrl;
	volatile unsigned time;
	volatile unsigned lstat;
	volatile unsigned bmAddrInit;
	volatile unsigned bmAddrLast;
	volatile unsigned bmAddrIrq;
	volatile unsigned bmAddrCur;
	volatile unsigned bmTimer;
	volatile unsigned rtMcc;
	volatile unsigned rtCfg;
	volatile unsigned rtAddr;
	volatile unsigned irqEna;
	volatile unsigned irqFlag;
	volatile unsigned revision;
} MilstdRegs;

#define MILSTD_CFG_BC_ENA           (1U << 31)
#define MILSTD_CFG_RT_ENA           (1U << 30)
#define MILSTD_CFG_BM_ENA           (1U << 29)
#define MILSTD_CFG_DB               (1U << 4)
#define MILSTD_CFG_ECO              (1U << 3)
#define MILSTD_CFG_MS_CONTROLLER    (1U << 2)
#define MILSTD_CFG_MS_TERMINAL      (1U << 2)
#define MILSTD_CFG_BE               (1U << 1)
#define MILSTD_CFG_BME              (1U << 0)

#define MILSTD_CTRL_TS_BUSY (1U << 2)
#define MILSTD_CTRL_TS_FREE (0U << 2)
#define MILSTD_CTRL_STOP    (1U << 1)
#define MILSTD_CTRL_RUN     (1U << 0)

#define MILSTD_TIME_IWGMIN(_x)  (((_x) & 0x1FF) << 20)
#define MILSTD_TIME_IWGMAX(_x)  (((_x) & 0x1FF) << 10)
#define MILSTD_TIME_IMG(_x)     (((_x) & 0x1FF) << 0)

#define MILSTD_BM_TIMER_UPD     (1U << 26)
#define MILSTD_BM_TIMER_CPT     (1U << 25)
#define MILSTD_BM_TIMER_LOAD    (1U << 25)
#define MILSTD_BM_TIMER_TMR(_x) ((_x) & 0xFFFFFF)

#define MILSTD_RT_MCC_SELECTED_TRANSMITTER_SHUTDOWN (1U << 20)
#define MILSTD_RT_MCC_TRANSMIT_BIT_WORD             (1U << 19)
#define MILSTD_RT_MCC_TRANSMIT_LAST_COMMAND         (1U << 18)
#define MILSTD_RT_MCC_SYNCHRONIZE_WITH_DATA_WORD    (1U << 17)
#define MILSTD_RT_MCC_TRANSMIT_VECTOR_WORD          (1U << 16)
#define MILSTD_RT_MCC_RESET_REMOTE_TERMINAL         (1U << 8)
#define MILSTD_RT_MCC_INHIBIT_TERMINAL_FLAG         (1U << 6)
#define MILSTD_RT_MCC_TRANSMITTER_SHUTDOWN          (1U << 4)
#define MILSTD_RT_MCC_INITIATE_SELF_TEST            (1U << 3)
#define MILSTD_RT_MCC_TRANSMIT_STATUS_WORD          (1U << 2)
#define MILSTD_RT_MCC_SYNCHRONIZE                   (1U << 1)
#define MILSTD_RT_MCC_DYNAMIC_BUS_CONTROL           (1U << 0)

#define MILSTD_RT_CFG_SW(_reg)      (((reg_) >> 16) & 0xFFFF)
#define MILSTD_RT_CFG_EDBC(_reg)    (((reg_) >> 9) & 1)
#define MILSTD_RT_CFG_RTACT(_reg)   (((reg_) >> 5) & 1)
#define MILSTD_RT_CFG_RTA(_reg)     (((reg_) >> 0) & 0x1F)

#define MILSTD_IRQ_ENA_BMED     (1U << 17)
#define MILSTD_IRQ_ENA_BMEBA    (1U << 16)
#define MILSTD_IRQ_ENA_RTED     (1U << 11)
#define MILSTD_IRQ_ENA_RTSYN    (1U << 10)
#define MILSTD_IRQ_ENA_RTERRT   (1U << 9)
#define MILSTD_IRQ_ENA_RTEDBC   (1U << 8)
#define MILSTD_IRQ_ENA_BCED     (1U << 2)
#define MILSTD_IRQ_ENA_BCER     (1U << 1)
#define MILSTD_IRQ_ENA_BCOC     (1U << 0)

#define MILSTD_IRQ_FLAG_BMID_DMA    MILSTD_IRQ_ENA_BMED
#define MILSTD_IRQ_FLAG_BMID_ADDR   MILSTD_IRQ_ENA_BMEBA
#define MILSTD_IRQ_FLAG_RTIRX       (1U << 13)
#define MILSTD_IRQ_FLAG_RTITX       (1U << 12)
#define MILSTD_IRQ_FLAG_RTID        MILSTD_IRQ_ENA_RTED
#define MILSTD_IRQ_FLAG_RTSYN       MILSTD_IRQ_ENA_RTSYN
#define MILSTD_IRQ_FLAG_RTRRT       MILSTD_IRQ_ENA_RTERRT
#define MILSTD_IRQ_FLAG_RTDBC       MILSTD_IRQ_ENA_RTEDBC
#define MILSTD_IRQ_FLAG_BCID        MILSTD_IRQ_ENA_BCED
#define MILSTD_IRQ_FLAG_BCIE        MILSTD_IRQ_ENA_BCER
#define MILSTD_IRQ_FLAG_BCIC        MILSTD_IRQ_ENA_BCOC

#endif /* HARDWARE_MILSTD_H_ */
