#ifndef HARDWARE_PLIC_H_
#define HARDWARE_PLIC_H_

typedef struct
{
	volatile unsigned ie;
	volatile unsigned thr;
	volatile unsigned cc;
	volatile unsigned msip;
	volatile unsigned _dummy[60];
} PlicTargetMap;

typedef struct
{
	volatile unsigned ip;
	volatile unsigned le;
	volatile unsigned prio[28];
	volatile unsigned _dummy[34];
	union
	{
		struct
		{
			PlicTargetMap cpu;
			PlicTargetMap fpga;
		};
		PlicTargetMap target[2];
	};
} PlicRegs;

#define PLIC_CC_OWI1    24
#define PLIC_CC_OWI0    23
#define PLIC_CC_CAN1    22
#define PLIC_CC_CAN0    21
#define PLIC_CC_MILSTD1 20
#define PLIC_CC_MILSTD0 19
#define PLIC_CC_SPW1    18
#define PLIC_CC_SPW0    17
#define PLIC_CC_I2C1    16
#define PLIC_CC_I2C0    15
#define PLIC_CC_SPI1    14
#define PLIC_CC_SPI0    13
#define PLIC_CC_UART1   12
#define PLIC_CC_UART0   11
#define PLIC_CC_TIMER2  10
#define PLIC_CC_TIMER1  9
#define PLIC_CC_TIMER0  8
#define PLIC_CC_STIMER  7
#define PLIC_CC_WDT     6
#define PLIC_CC_FPGA    5
#define PLIC_CC_CMM     4
#define PLIC_CC_SCRUB   3
#define PLIC_CC_GPIOB   2
#define PLIC_CC_GPIOA   1

#define PLIC_IP_OWI1    (1U << PLIC_CC_OWI1)
#define PLIC_IP_OWI0    (1U << PLIC_CC_OWI0)
#define PLIC_IP_CAN1    (1U << PLIC_CC_CAN1)
#define PLIC_IP_CAN0    (1U << PLIC_CC_CAN0)
#define PLIC_IP_MILSTD1 (1U << PLIC_CC_MILSTD1)
#define PLIC_IP_MILSTD0 (1U << PLIC_CC_MILSTD0)
#define PLIC_IP_SPW1    (1U << PLIC_CC_SPW1)
#define PLIC_IP_SPW0    (1U << PLIC_CC_SPW0)
#define PLIC_IP_I2C1    (1U << PLIC_CC_I2C1)
#define PLIC_IP_I2C0    (1U << PLIC_CC_I2C0)
#define PLIC_IP_SPI1    (1U << PLIC_CC_SPI1)
#define PLIC_IP_SPI0    (1U << PLIC_CC_SPI0)
#define PLIC_IP_UART1   (1U << PLIC_CC_UART1)
#define PLIC_IP_UART0   (1U << PLIC_CC_UART0)
#define PLIC_IP_TIMER2  (1U << PLIC_CC_TIMER2)
#define PLIC_IP_TIMER1  (1U << PLIC_CC_TIMER1)
#define PLIC_IP_TIMER0  (1U << PLIC_CC_TIMER0)
#define PLIC_IP_STIMER  (1U << PLIC_CC_STIMER)
#define PLIC_IP_WDT     (1U << PLIC_CC_WDT)
#define PLIC_IP_FPGA    (1U << PLIC_CC_FPGA)
#define PLIC_IP_CMM     (1U << PLIC_CC_CMM)
#define PLIC_IP_SCRUB   (1U << PLIC_CC_SCRUB)
#define PLIC_IP_GPIOB   (1U << PLIC_CC_GPIOB)
#define PLIC_IP_GPIOA   (1U << PLIC_CC_GPIOA)

#define PLIC_LE_OWI1    PLIC_IP_OWI1
#define PLIC_LE_OWI0    PLIC_IP_OWI0
#define PLIC_LE_CAN1    PLIC_IP_CAN1
#define PLIC_LE_CAN0    PLIC_IP_CAN0
#define PLIC_LE_MILSTD1 PLIC_IP_MILSTD1
#define PLIC_LE_MILSTD0 PLIC_IP_MILSTD0
#define PLIC_LE_SPW1    PLIC_IP_SPW1
#define PLIC_LE_SPW0    PLIC_IP_SPW0
#define PLIC_LE_I2C1    PLIC_IP_I2C1
#define PLIC_LE_I2C0    PLIC_IP_I2C0
#define PLIC_LE_SPI1    PLIC_IP_SPI1
#define PLIC_LE_SPI0    PLIC_IP_SPI0
#define PLIC_LE_UART1   PLIC_IP_UART1
#define PLIC_LE_UART0   PLIC_IP_UART0
#define PLIC_LE_TIMER2  PLIC_IP_TIMER2
#define PLIC_LE_TIMER1  PLIC_IP_TIMER1
#define PLIC_LE_TIMER0  PLIC_IP_TIMER0
#define PLIC_LE_STIMER  PLIC_IP_STIMER
#define PLIC_LE_WDT     PLIC_IP_WDT
#define PLIC_LE_FPGA    PLIC_IP_FPGA
#define PLIC_LE_CMM     PLIC_IP_CMM
#define PLIC_LE_SCRUB   PLIC_IP_SCRUB
#define PLIC_LE_GPIOB   PLIC_IP_GPIOB
#define PLIC_LE_GPIOA   PLIC_IP_GPIOA

#define PLIC_IE_OWI1    PLIC_IP_OWI1
#define PLIC_IE_OWI0    PLIC_IP_OWI0
#define PLIC_IE_CAN1    PLIC_IP_CAN1
#define PLIC_IE_CAN0    PLIC_IP_CAN0
#define PLIC_IE_MILSTD1 PLIC_IP_MILSTD1
#define PLIC_IE_MILSTD0 PLIC_IP_MILSTD0
#define PLIC_IE_SPW1    PLIC_IP_SPW1
#define PLIC_IE_SPW0    PLIC_IP_SPW0
#define PLIC_IE_I2C1    PLIC_IP_I2C1
#define PLIC_IE_I2C0    PLIC_IP_I2C0
#define PLIC_IE_SPI1    PLIC_IP_SPI1
#define PLIC_IE_SPI0    PLIC_IP_SPI0
#define PLIC_IE_UART1   PLIC_IP_UART1
#define PLIC_IE_UART0   PLIC_IP_UART0
#define PLIC_IE_TIMER2  PLIC_IP_TIMER2
#define PLIC_IE_TIMER1  PLIC_IP_TIMER1
#define PLIC_IE_TIMER0  PLIC_IP_TIMER0
#define PLIC_IE_STIMER  PLIC_IP_STIMER
#define PLIC_IE_WDT     PLIC_IP_WDT
#define PLIC_IE_FPGA    PLIC_IP_FPGA
#define PLIC_IE_CMM     PLIC_IP_CMM
#define PLIC_IE_SCRUB   PLIC_IP_SCRUB
#define PLIC_IE_GPIOB   PLIC_IP_GPIOB
#define PLIC_IE_GPIOA   PLIC_IP_GPIOA

#define PLIC_MSIP_MSIP  1U

#endif /* HARDWARE_PLIC_H_ */
