#ifndef HARDWARE_TIMER_H_
#define HARDWARE_TIMER_H_

typedef struct
{
	volatile unsigned char tim0Cfg0;
	volatile unsigned char tim0Cfg1;
	volatile unsigned char tim0Cfg2;
	volatile unsigned char : 8;
	volatile unsigned char tim0Ctrl;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char ctrl0;
	volatile unsigned char ctrl1;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char tim0Load0;
	volatile unsigned char tim0Load1;
	volatile unsigned char tim0Load2;
	volatile unsigned char tim0Load3;
	volatile unsigned char tim0Cd;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char tim0Value0;
	volatile unsigned char tim0Value1;
	volatile unsigned char tim0Value2;
	volatile unsigned char tim0Value3;
	volatile unsigned char tim0Cpt0;
	volatile unsigned char tim0Cpt1;
	volatile unsigned char tim0Cpt2;
	volatile unsigned char tim0Cpt3;
	volatile unsigned char ie0;
	volatile unsigned char ie1;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char if0;
	volatile unsigned char if1;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char tim0CmpaT00;
	volatile unsigned char tim0CmpaT01;
	volatile unsigned char tim0CmpaT02;
	volatile unsigned char tim0CmpaT03;
	volatile unsigned char tim0CmpaT10;
	volatile unsigned char tim0CmpaT11;
	volatile unsigned char tim0CmpaT12;
	volatile unsigned char tim0CmpaT13;
	volatile unsigned char tim0CmpbT00;
	volatile unsigned char tim0CmpbT01;
	volatile unsigned char tim0CmpbT02;
	volatile unsigned char tim0CmpbT03;
	volatile unsigned char tim0CmpbT10;
	volatile unsigned char tim0CmpbT11;
	volatile unsigned char tim0CmpbT12;
	volatile unsigned char tim0CmpbT13;
	volatile unsigned char tim0CmpcT00;
	volatile unsigned char tim0CmpcT01;
	volatile unsigned char tim0CmpcT02;
	volatile unsigned char tim0CmpcT03;
	volatile unsigned char tim0CmpcT10;
	volatile unsigned char tim0CmpcT11;
	volatile unsigned char tim0CmpcT12;
	volatile unsigned char tim0CmpcT13;

	volatile unsigned char tim1Cfg0;
	volatile unsigned char tim1Cfg1;
	volatile unsigned char tim1Cfg2;
	volatile unsigned char : 8;
	volatile unsigned char tim1Ctrl;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char tim1Load0;
	volatile unsigned char tim1Load1;
	volatile unsigned char tim1Load2;
	volatile unsigned char tim1Load3;
	volatile unsigned char tim1Cd;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char tim1Value0;
	volatile unsigned char tim1Value1;
	volatile unsigned char tim1Value2;
	volatile unsigned char tim1Value3;
	volatile unsigned char tim1Cpt0;
	volatile unsigned char tim1Cpt1;
	volatile unsigned char tim1Cpt2;
	volatile unsigned char tim1Cpt3;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char : 8;
	volatile unsigned char tim1CmpaT00;
	volatile unsigned char tim1CmpaT01;
	volatile unsigned char tim1CmpaT02;
	volatile unsigned char tim1CmpaT03;
	volatile unsigned char tim1CmpaT10;
	volatile unsigned char tim1CmpaT11;
	volatile unsigned char tim1CmpaT12;
	volatile unsigned char tim1CmpaT13;
	volatile unsigned char tim1CmpbT00;
	volatile unsigned char tim1CmpbT01;
	volatile unsigned char tim1CmpbT02;
	volatile unsigned char tim1CmpbT03;
	volatile unsigned char tim1CmpbT10;
	volatile unsigned char tim1CmpbT11;
	volatile unsigned char tim1CmpbT12;
	volatile unsigned char tim1CmpbT13;
	volatile unsigned char tim1CmpcT00;
	volatile unsigned char tim1CmpcT01;
	volatile unsigned char tim1CmpcT02;
	volatile unsigned char tim1CmpcT03;
	volatile unsigned char tim1CmpcT10;
	volatile unsigned char tim1CmpcT11;
	volatile unsigned char tim1CmpcT12;
	volatile unsigned char tim1CmpcT13;
} TimerRegs;

#define TIMER_CFG0_CMP_TYPE_INVERSION   (2U << 6)
#define TIMER_CFG0_CMP_TYPE_SWITCH_TO_0 (1U << 6)
#define TIMER_CFG0_CMP_TYPE_SWITCH_TO_1 (0U << 6)
#define TIMER_CFG0_CMP_EN_ABC           (7U << 3)
#define TIMER_CFG0_CMP_EN_BC            (6U << 3)
#define TIMER_CFG0_CMP_EN_AC            (5U << 3)
#define TIMER_CFG0_CMP_EN_C             (4U << 3)
#define TIMER_CFG0_CMP_EN_AB            (3U << 3)
#define TIMER_CFG0_CMP_EN_B             (2U << 3)
#define TIMER_CFG0_CMP_EN_A             (1U << 3)
#define TIMER_CFG0_MODE_COUNTER         (4U << 0)
#define TIMER_CFG0_MODE_COMPARE         (2U << 0)
#define TIMER_CFG0_MODE_CAPTURE         (1U << 0)
#define TIMER_CFG0_MODE_TIMER           (1U << 0)

#define TIMER_CFG1_CPT_STOP_ANYEDGE     (3U << 5)
#define TIMER_CFG1_CPT_STOP_NEGEDGE     (2U << 5)
#define TIMER_CFG1_CPT_STOP_POSEDGE     (1U << 5)
#define TIMER_CFG1_CPT_STOP_TIMER       (0U << 5)
#define TIMER_CFG1_CPT_START_ANYEDGE    (3U << 3)
#define TIMER_CFG1_CPT_START_NEGEDGE    (2U << 3)
#define TIMER_CFG1_CPT_START_POSEDGE    (1U << 3)
#define TIMER_CFG1_CPT_START_EN         (0U << 3)
#define TIMER_CFG1_CPT_TYPE_ANYEDGE     (3U << 1)
#define TIMER_CFG1_CPT_TYPE_4POSEDGE    (2U << 1)
#define TIMER_CFG1_CPT_TYPE_NEGEDGE     (1U << 1)
#define TIMER_CFG1_CPT_TYPE_POSEDGE     (0U << 1)
#define TIMER_CFG1_CPT_SEL_CPT1         (1U << 0)
#define TIMER_CFG1_CPT_SEL_CPT0         (0U << 0)

#define TIMER_CFG2_ASYNC_SRC_CPT_SEL_ASYNC_CMPB (7U << 5)
#define TIMER_CFG2_ASYNC_SRC_CPT_SEL_ASYNC_CMPA (6U << 5)
#define TIMER_CFG2_ASYNC_SRC_CPT_SEL_PLL        (5U << 5)
#define TIMER_CFG2_ASYNC_SRC_CPT_SEL_LRC        (4U << 5)
#define TIMER_CFG2_ASYNC_SRC_CPT_SEL_HRC        (3U << 5)
#define TIMER_CFG2_ASYNC_SRC_CPT_SEL_XTAL       (2U << 5)
#define TIMER_CFG2_ASYNC_SRC_CPT_SEL_EXT        (1U << 5)
#define TIMER_CFG2_ASYNC_SRC_CPT_SEL_GPIO       (0U << 5)
#define TIMER_CFG2_SYNC_SRC_CPT_SEL_CMP         (3U << 3)
#define TIMER_CFG2_SYNC_SRC_CPT_SEL_SYNC_CMPB   (2U << 3)
#define TIMER_CFG2_SYNC_SRC_CPT_SEL_SYNC_CMPA   (1U << 3)
#define TIMER_CFG2_SYNC_SRC_CPT_SEL_SLEEP       (0U << 3)
#define TIMER_CFG2_ONESHOT_ONETIME              (1U << 1)
#define TIMER_CFG2_ONESHOT_PERIODIC             (0U << 1)
#define TIMER_CFG2_DIR_INC                      (1U << 0)
#define TIMER_CFG2_DIR_DEC                      (0U << 0)

#define TIMER_CTRL_CPT      (1U << 2)
#define TIMER_CTRL_PAUSE    (1U << 1)
#define TIMER_CTRL_EN       (1U << 0)

#define TIMER_ALL_CTRL0_TIMER1_PAUSE    (1U << 3)
#define TIMER_ALL_CTRL0_TIMER1_EN       (1U << 2)
#define TIMER_ALL_CTRL0_TIMER0_PAUSE    (1U << 1)
#define TIMER_ALL_CTRL0_TIMER0_EN       (1U << 0)

#define TIMER_ALL_CTRL1_TIMER1_CPT  (1U << 1)
#define TIMER_ALL_CTRL1_TIMER0_CPT  (1U << 0)

#define TIMER_IE0_CPT1  (1U << 5)
#define TIMER_IE0_CPT0  (1U << 4)
#define TIMER_IE0_END1  (1U << 1)
#define TIMER_IE0_END0  (1U << 0)

#define TIMER_IE1_CMP1  (1U << 1)
#define TIMER_IE1_CMP0  (1U << 0)

#define TIMER_IF0_CPT1  TIMER_IE0_CPT1
#define TIMER_IF0_CPT0  TIMER_IE0_CPT0
#define TIMER_IF0_END1  TIMER_IE0_END1
#define TIMER_IF0_END0  TIMER_IE0_END0

#define TIMER_IF1_CMP1  TIMER_IE1_CMP1
#define TIMER_IF1_CMP0  TIMER_IE1_CMP0

#endif /* HARDWARE_TIMER_H_ */
